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Experimental Results
In this section, we present experimental
results for the proposed techniques which are implemented as
described in Section VI. As mentioned before, the
wire capacitances are taken from [43] which are
themselves based on the information in [63]. The
circuits were synthesized using an RTL design library based on NEC
0.18m technology [44,45]. SCALP, the
high-level synthesis tool, on top of which we implemented our
techniques, already has the capability to optimize circuits for
area and power, however, in an interconnect-unaware fashion. Such
SCALP-generated circuits are used for comparisons. All the
circuits are given the same performance constraint, , 1.2.
Indeed, a benchmark circuit is enforced to have the same
performance for different optimizations for fair comparison.
The experiments were conducted on a 1.3 GHz Pentium IV based PC
with 256 MB memory. The CPU times for high-level synthesis vary
from less than one second for Diffeq to 207 seconds for
Jacobi. The CPU times for CDFG and RTL simulation are
proportional to the size of the input traces. In our experiments,
they are comparable to CPU times of high-level synthesis.
Subsections
Next: Interconnect-aware high-level synthesis
Up: Interconnect-aware Low Power High-level
Previous: interconnect-aware high-level synthesis for
Lin Zhong
2003-10-11