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Interconnect power reduction

Fig. 15 presents interconnect power reduction of IAPO-gated circuits compared to AO, IUPO and IAPO circuits. The average reductions are 72.9%, 53.1% and 15.7%, respectively. This shows that our interconnect power reduction techniques are quite effective. Since our methodology is to trade some DPU power savings for more interconnect power savings, when interconnects consume a higher fraction of total circuit power in future technologies and larger designs, our methodology is likely to yield a higher total circuit power reduction.
Figure 15: Interconnect power reduction.
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To better illustrate the effectiveness of the proposed techniques, Fig. 16 shows the length and corresponding unit-length power consumption of individual inter-DPU data transfers for the IUPO, IAPO, and IAPO-gated implementations of the $Elliptic$ benchmark. It also shows the square root of the circuit area (the solid line for IUPO and dashed for IAPO) for reference. A data transfer is performed on a multi-bit wire connecting two DPUs. One can see that compared to IUPO circuits, only shorter wires have high unit-length power in IAPO circuits. The unit-length power of these wires is further reduced in IAPO-gated circuits. Fig. 17 redraws the data in Fig. 16 as distributions of individual data transfer power for different implementations. The $y$ co-ordinate specifies the fraction of all data transfers that consume power rounded to the number given by the $x$ co-ordinate. These figures demonstrate that interconnect-aware high-level synthesis and signal gating drastically reduce the length of high unit-length power data transfers and the number of high-power data transfers. It should be noted that the IUPO implementation of $Elliptic$ has 88 inter-DPU data transfers while IAPO and IAPO-gated implementations only have 78.
Figure 16: Data transfer wire length and corresponding unit-length data transfer power for $Elliptic$ when optimized under different scenarios.
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Figure 17: Data transfer power distribution for $Elliptic$ under different scenarios.
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next up previous
Next: Total power reduction Up: Experimental Results Previous: Gating signals with SSA
Lin Zhong 2003-10-11