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Total power reduction

Fig. 18 shows the percentage power reduction and area overhead when all the proposed techniques are applied ($i.e.$, for IAPO-gated circuits) compared to IUPO and AO circuits. The area overhead for some benchmarks is negative, which means the proposed techniques also reduced the circuit area. For all the benchmarks, an average 26.8% total power reduction is achieved compared to IUPO circuits with 0.5% area overhead. Compared to AO circuits, the average power reduction is 56.0% with 44.4% average area overhead.
Figure 18: Total power reduction and area overhead.
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It is worth noting that compared with that of AO circuits, interconnect power of IAPO ones is significantly reduced in spite of the area increase. Intuitively, bigger circuits would be expected to have longer interconnects and to spend more power in them. In IAPO circuits, however, our techniques tried to ensure that units exchanging high-switching data can be floorplanned as close to each other as possible, reduce switching activity for data transfer, and also minimize the number of long data-transfer wires. Therefore, although we have a bigger circuit, we have fewer power-hungry interconnects and fewer long interconnects as shown in Figures 16 and  17. In the case of IAPO circuits, interconnect topology and switching activity distribution is optimized. This is why interconnect power consumption is reduced even when circuit area is increased.
next up previous
Next: Commercial tools Up: Experimental Results Previous: Interconnect power reduction
Lin Zhong 2003-10-11